#Cpu transistor count history software
“The GDXC is a valuable tool for system and software debuggers,” Knoll said. The bus, dubbed the Generic Debug eXternal Connection (GDXC), allows chip, system or software debuggers to sample ring data traffic as well as ring protocol control signals and drive it to an external logic analyzer, where it can be recovered and analyzed, according to the paper.
Sandy Bridge also introduces a debug bus that allows monitoring the traffic between the x86 cores, GPU, caches and system agent on the processor internal ring, according to the paper. Thanks to the use of these design techniques, Sandy Bridge's power dissipation ranges from 95W for a four-core device operating in a high-end desktop to17W for a two-core Sandy Bridge running an optimized mobile product, according to the paper. “With such techniques we are able to improve the minimum operating voltage for a vast majority” of the chip, Knoll said.
One of the techniques used to skirt the issue was a shared p-channel MOSFET technique that weakens the memory cell pull up device effective strength that solves the problem of RF write-ability degradation at low voltages that can be created by manufacturing process variations, Knoll said. “One of the design targets was to minimize as much as possible power consumption,” Knoll said. Intel got around this issue by developing several circuit and logic design techniques to minimize the minimum operational voltage of the 元 cache and the register files of the chip to bring it to a lower level than the core logic, according to the paper. Also, the devices' CPUs and GPU share the same 8MB level-3 cache memory, according to the paper.īecause Sandy Bridges' x86 cores and 元 cache share the same power plane, Intel faced the challenge that the minimum voltage needed to keep the 元 cache data may have limited the minimum operating voltage of the cores, increasing the power consumption of the system, according to the paper. The Sandy Bridge IA core implements several improvements that boost performance without increasing power consumption, including an improved branch prediction algorithm, a micro-operation cache and a floating point advanced vector extension, according to the paper. Sandy Bridge features 1.16 billion transistors and a die size of 216 square millimeters, Knoll said. The 32-nm Sandy Bridge processor integrates up to four x86 cores, a power/performance optimized graphic processing unit (GPU) and DDR3 memory and PCI Express controllers on the same die, according to the paper presented at ISSCC Tuesday by Ernest Knoll, a designer at Intel's design center in Haifa, Israel. 22), including further description of its modular ring interconnect, design techniques used to minimize the cache's operational voltage and the inclusion of debug bus for monitoring traffic on the interconnect. disclosed more technical details of its 32-nm Sandy Bridge processor at the International Solid-State Circuits Conference here Tuesday (Feb.
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